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m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 1 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. based on ddr2 - 667 /800 64mx16 ( 1gb)/ 128 mx8 ( 2gb) sdram g - die features ? performance: speed sort pc2 - 5300 pc2 - 6400 unit - 3c - ac dimm cas latency 5 5 fck C C ? 20 0 - pin small outline dual in - line memory module (so - dimm) ? 1gb: 128 mx64 unbuffered ddr 2 s o - dimm based on 64 m x16 ddr 2 sdram g - die devices . ? 2gb: 256 mx64 unbuffered ddr 2 s o - dimm based on 128m x8 ddr 2 sdram g - die devices . ? intended for 333 mhz and 400mhz a pplications ? inputs and outputs are sstl - 18 compatible ? v dd = v ddq = 1.8v ? 0.1v ? sdrams have 8 internal banks for concurrent operation ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs transitions with clock t ransitions. ? address and control signals are fully synchronous to positive clock edge ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? programmable operation: - dimm ??? latency: 3, 4 , 5 - burst type: sequential or interleave - burst length: 4, 8 - operation: burst read and write ? 1 3 /10/2 addressing ( 1g b ) ? 1 4 /10/2 addressing (2g b ) ? 7.8 ? s max. average periodic refresh interval ? serial presence detect ? gold contacts ? 1gb module s sdrams are 84 - ba ll bga package ? 2gb module s sdrams are 60 - ball bga package ? rohs complian ce description m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B are unbuffe r ed 200 - pin double data rate 2 (ddr 2 ) synchronous dram small outline dual in - line memory module ( s o - dimm), organized as two ranks of 128mx64 ( 1gb) / 256mx64 ( 2gb) high - speed memory array. m2n1g 64tuh8g5 f / m2s1g64tuh8g4f use s eight 64mx16 84 - ball bga packaged devices and m2n2g64tu8h g5 b / M2N2G64TU8HG4B use s sixteen 128mx8 60 - ball bga packaged devices. these dimms are manu factured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical variation between suppliers. all elixir ddr 2 so dimms provide a high - performance, flexible 8 - byte interface in a space - saving footprint. the dimm is intended for use in applications operating of 333 mhz / 400mhz clock speeds and achieves high - speed data transfer speed of 667 mbps/800mbps . prior to any access operation, the device ??? latency and burst /length/operation type mus t be programmed into the dimm by address inputs a0 - a1 2 (1gb) / a0 - a13 (2gb) and i/o inputs ba0 , ba1 and ba 2 using the mode register set cycle. the dimm uses serial presence - detect implemented via a serial eeprom using a standard iic protocol. the first 128 bytes of s pd data are programmed and locked during module assembly. the remaining 128 bytes are available for use by the customer.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 2 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ordering information part number speed organization power leads note m2n2g 64tu8hg5 b - ac ddr2 - 800 pc2 - 6400 400mhz (2.5ns @ cl = 5) 256mx64 1.8v gold m2n2g 64tu8hg5 b - 3c ddr2 - 667 pc2 - 53 00 333 mhz ( 3 .0ns @ cl = 5) M2N2G64TU8HG4B - ac ddr2 - 800 pc2 - 6400 400mhz (2.5ns @ cl = 5) m2n1g 64tuh8g5 f - ac ddr2 - 800 pc2 - 6400 400mhz (2.5ns @ cl = 5) 128mx64 m2n1g 64tuh8g5 f - 3c ddr2 - 6 67 pc2 - 53 00 333 mhz ( 3 .0ns @ cl = 5) m2s1g64tuh8g4f - ac ddr2 - 800 pc2 - 6400 400mhz (2.5ns @ cl = 5) pin description ck0 , ck1 , ??? , ??? differential clock inputs dq0 - dq63 data input/output cke0 , cke1 clock enable dqs0 - dqs7 bidirectional data strobes ??? row address strobe ???? - ???? differential data strobes ??? column address strobe dm0 - dm7 input data masks ?? write enable v dd power ( 1.8 v) ??? , ??? chip selects v ref ref. voltage for sstl_18 inputs a0 - a9 a11 - a1 3 row address inputs v ddspd serial eeprom positive power supply a0 - a9 column address inputs v ss ground a10/ap column address input/auto - precharge scl serial presence detect clock input ba0, ba1 , ba2 sdram bank address inputs sda serial presence detect data input/output odt0, odt1 active termination control lines sa0, sa1 serial presence detect address inputs nc no connect note: a13 is for 2gb modules only.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 3 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. pinou t pin front pin back pin front pin back pin front pin back pin front pin back 1 v ref 2 v ss 51 dqs2 52 dm2 101 a1 102 a0 151 dq42 152 dq46 3 v ss 4 dq 4 53 v ss 54 v ss 103 v dd 104 v dd 153 dq43 154 dq47 5 dq 0 6 dq 5 55 dq18 56 dq22 105 a10/ap 106 ba1 155 v ss 156 v ss 7 dq 1 8 v ss 57 dq19 58 dq23 107 ba0 108 ??? ? 157 dq48 158 dq52 9 v ss 10 dm0 59 v ss 60 v ss 109 ?? ? 110 ??? ? 159 dq49 160 dq53 11 ???? ? 12 v ss 61 dq24 62 dq28 111 v dd 112 v dd 161 v ss 162 v ss 13 dq s0 14 dq6 63 dq25 64 dq29 113 ??? ? 114 odt0 163 nc 164 ck1 15 v ss 16 dq7 65 v ss 66 v ss 115 ??? ? 116 a13 /nc 165 v ss 166 ??? ? 17 dq2 18 v ss 67 dm3 68 ???? ? 117 v dd 118 v dd 167 ???? ? 168 v ss 19 dq3 20 dq12 69 nc 70 dqs3 119 odt1 120 nc 169 dqs6 170 dm6 21 v ss 22 dq13 71 v ss 72 v ss 121 v ss 122 v ss 171 v ss 172 v ss 23 dq8 24 v ss 73 dq26 74 dq30 123 dq32 124 dq36 173 dq50 174 dq54 25 dq9 26 dm1 75 dq27 76 dq31 125 dq33 126 dq37 175 dq51 176 dq55 27 v ss 28 v ss 77 v ss 78 v ss 127 v ss 128 v ss 177 v ss 178 v ss 29 ???? ? 30 ck0 79 cke0 80 cke1 129 ???? ? 130 dm4 179 dq56 180 dq60 31 dqs1 32 ??? ? 81 v dd 82 v dd 131 dqs4 132 v ss 181 dq57 182 dq61 33 v ss 34 v ss 83 nc 84 nc 133 v ss 134 dq38 183 v ss 184 v ss 35 dq10 36 dq14 85 ba2 86 nc 135 dq34 136 dq39 185 dm7 186 ???? ? 37 dq11 38 dq15 87 v dd 88 v dd 137 dq35 138 v ss 187 v ss 188 dqs7 39 v ss 40 v ss 89 a1 2 90 a1 1 139 v ss 140 dq44 189 dq58 190 v ss 41 v ss 42 v ss 91 a9 92 a7 141 dq40 142 dq45 191 dq59 192 dq62 43 dq16 44 dq20 93 a8 94 a6 143 dq41 144 v ss 193 v ss 194 dq63 45 dq17 46 dq21 95 v dd 96 v dd 145 v ss 146 ???? ? 195 sda 196 v s s 47 v ss 48 v ss 97 a5 98 a4 147 dm5 148 dqs5 197 scl 198 sa0 49 ???? ? 50 nc 99 a3 100 a2 149 v ss 150 v ss 199 v ddspd 200 sa1 note: all pin assignments are consistent for all 8 - byte unbuffered versions. a13 is for 2gb modules only.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 4 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0 , ck1 (sstl) positive edge the positive line of the differential pair of system clock inputs which drives the input to the on - dimm pll. all the ddr 2 sdram address and control inputs are sampled on t he rising edge of their associated clocks. ??? , ??? (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on - dimm pll. cke0 , cke1 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by dea ctivating the clocks, cke low initiates the power down mode, or the self refresh mode. ??? , ??? (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ??? , ??? , ?? (sstl) active low when sampled at the positive rising edge of the clock, ??? , ??? , ?? define the operation to be executed by the sdram. v ref supply reference voltage for sstl - 18 inputs odt0, odt1 input active high on - die termination control signals ba0, ba1 , ba2 (sstl) - selects which sdram bank is to be active. a0 C a9 a10/ap a11 , a12/a13 (sstl) - during a bank activate command cycle, a0 - a1 2/a13 define the row address (ra0 - ra1 2/ra1 3 ) when sampled at the rising clock edge. a13 applies on 2gb sodimm only. during a read or write command cycle, a0 - a 9 defines the column address (ca0 - ca 9 ) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autopr echarge operation at the end of the burst read or write cycle. if ap is high, a utoprecharge is selected and ba0/ba1 /ba2 define the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction w ith ba0/ba1 /ba2 to control which bank(s) to precharge. if ap is high all 8 banks will be precharged regardless of the state of ba0/ba1 /ba2 . if ap is low, then ba0/ba1 /ba2 are used to define which bank to pre - charge. dq0 C dq 63 (sstl) active high data and check bit input/output pins. v dd , v ss supply power and ground for the ddr2 sdram input buffers and core logic dq s 0 C dq s7 ???? C ???? (sstl) negative and positive edge data strobe for input and output data dm0 C dm 7 input active high the data write m asks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dm8 is associated with check bits cb0 - cb7, and is not used on x64 modules. sa0 C sa 1 - address inputs. connected to either v dd or v ss on the system board to configure the serial presence detect eeprom address. sda - this bi - directional pin is used to transfer data into or out of the spd eeprom . a resistor must be connected from the sda bus line to v dd to act as a pull - up. scl - this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pull - up. v ddspd supply seria l eeprom positive power supply.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 5 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram [ 1g b C 2 r ank s , 64 mx16 ddr 2 sd rams ] v d d s p d v s s s p d v d d v r e f v d d i d n o t e s : 1 . d q w i r i n g m a y d i f f e r f r o m t h a t d e s c r i b e d i n t h i s d r a w i n g . 2 . d q / d q s / d m / c k e / s s r e l a t i o n s h i p s a r e m a i n t a i n e d a s s h o w n . 3 . d q / d q s / d m / d q s r e s i s t o r s a r e 2 2 + / - 5 % o h m s 4 . v d d i d s t r a p c o n n e c t i o n s ( f o r m e m o r y d e v i c e v d d , v d d q ) : s t r a p o u t ( o p e n ) : v d d = v d d q s t r a p i n ( v s s ) : v d d i s n o t e q u a l t o v d d q 4 l o a d s c k 0 ? ? ? c k 1 ? ? ? 4 l o a d s s e r i a l p d a 0 a 2 a 1 s c l w p s d a s a 0 s a 1 ? ? ? d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 d q s 6 d m 6 d q s 7 d m 7 ? ? ? ? ? ? ? ? d m 4 d q s 4 d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 d q s 5 d m 5 ? ? ? ? ? ? ? ? ? ? ? d m 0 d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 d q s 0 d m 1 d q s 1 ? ? ? ? ? ? ? ? i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 0 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? d m 3 ? ? ? ? d m 2 d q s 2 d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 ? ? ? ? d q s 3 o d t 1 o d t 0 c k e 1 c k e 0 c k e o d t 3 o h m s + / - 5 % b a 0 - b a 2 a 0 - a 1 2 ? ? ? s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 ? ? ? ? ? s d r a m s d 0 - d 7 s d r a m s d 0 - d 7 s a 0 s a 1 d 0 - d 7 , v d d a n d v d d q d 0 - d 7 d 0 - d 7 , s p d i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 4 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 1 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 5 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 2 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 3 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 6 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 l d m ? ? d 7 i / o 8 i / o 9 i / o 1 4 i / o 1 3 i / o 1 2 i / o 1 1 i / o 1 0 i / o 1 5 u d m u d q s l d q s ? ? ? ? ? ? ? ? c k e o d t
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 6 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. functional block diagram [ 2 g b C 2 r ank s , 128 m x8 ddr 2 sdrams ] n o t e s : u n l e s s o t h e r w i s e n o t e d , r e s i s t o r v a l u e s a r e 2 2 o h m s + / - 5 % d q w i r i n g w a y d i f f e r f r o m t h a t d e s c r i b e d i n t h i s d r a w i n g ; d e s c r i b e d i n t h i s d r a w i n g ; h o w e v e r , d q / d m / d q s / d q s r e l a t i o n s h i p s a r e m a i n t a i n e d a s s h o w n s e r i a l p d a 0 a 2 a 1 s c l w p s d a c s 0 c s 1 o d t 1 o d t 0 c k e 1 c k e 0 3 o h m s + / - 5 % s a 0 s a 1 s c l v d d s p d v s s s e r i a l p d s d r a m s d 0 - d 1 5 , v d d , a n d v d d q v d d v r e f s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 , s p d b a 0 - b a 2 a 0 - a 1 3 r a s s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 w e c a s s d r a m s d 0 - d 1 5 s d r a m s d 0 - d 1 5 1 0 o h m s + / - 5 % d m 0 d q 0 d q 1 d q 2 d q 7 d q 4 d q 6 d q 5 d q 3 d q s 0 d q s 0 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m c s 0 d 0 , d 8 d q s d q s c k e 0 c k e 1 o d t 1 o d t 0 c s 1 d m 1 d q 8 d q 9 d q 1 0 d q 1 5 d q 1 2 d q 1 4 d q 1 3 d q 1 1 d q s 1 d q s 1 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 1 , d 9 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 2 d q 1 6 d q 1 7 d q 1 8 d q 2 3 d q 2 0 d q 2 2 d q 2 1 d q 1 9 d q s 2 d q s 2 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 2 , d 1 0 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 3 d q 2 4 d q 2 5 d q 2 6 d q 3 1 d q 2 8 d q 3 0 d q 2 9 d q 2 7 d q s 3 d q s 3 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 3 , d 1 1 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 4 d q 3 2 d q 3 3 d q 3 4 d q 3 9 d q 3 6 d q 3 8 d q 3 7 d q 3 5 d q s 4 d q s 4 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 4 , d 1 2 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 5 d q 4 0 d q 4 1 d q 4 2 d q 4 7 d q 4 4 d q 4 6 d q 4 5 d q 4 3 d q s 5 d q s 5 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 5 , d 1 3 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 6 d q 4 8 d q 4 9 d q 5 0 d q 5 5 d q 5 2 d q 5 4 d q 5 3 d q 5 1 d q s 6 d q s 6 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 6 , d 1 4 d q s c k e 0 c k e 1 o d t 1 o d t 0 d m 7 d q 5 6 d q 5 7 d q 5 8 d q 6 3 d q 6 0 d q 6 2 d q 6 1 d q 5 9 d q s 7 d q s 7 i / o 0 i / o 1 i / o 6 i / o 5 i / o 4 i / o 3 i / o 2 i / o 7 d m d 7 , d 1 5 d q s c k e 0 c k e 1 o d t 1 o d t 0 8 l o a d s c k 0 c k 0 5 . 6 p f 8 l o a d s c k 1 5 . 6 p f c k 1 c s 0 d q s c s 1 c s 0 d q s c s 1 c s 0 d q s c s 1 c s 0 d q s c s 1 c s 0 d q s c s 1 c s 0 d q s c s 1 c s 0 d q s c s 1
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 7 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detec t (1gb C 2 ra nks, 64mx16 ddr2 sdrams) (part 1 of 2) byte description serial pd data entry (hex.) note - 3c - ac 0 number of serial pd bytes written during production 80 80 1 total number of bytes in serial pd device 08 08 2 fundamental memory type 08 08 3 num ber of row addresses on assembly 0d 0d 4 number of column addresses on assembly 0a 0a 5 number of dimm rank s , package, and height 61 61 6 data width of assembly 40 40 7 reserved 00 00 8 voltage interface level of this assembly 05 05 9 ddr2 sdra m device cycle time at cl=5 30 25 10 ddr2 sdram device access time (t ac ) from clock at cl=5 45 40 11 dimm configuration type 00 00 12 refresh rate/type 82 82 13 primary ddr 2 sdram width 10 10 14 error checking ddr 2 sdram device width 00 00 15 r eserved 00 00 16 ddr2 sdram device attributes: burst length supported 0c 0c 17 ddr2 sdram device attributes: number of device banks 08 08 18 ddr2 sdram device attributes: ??? latencies supported 38 38 19 dimm mechanical characteristics 01 01 20 ddr2 sdram dimm type information 04 04 21 ddr2 sdram module attributes 00 00 22 ddr2 sdram device attributes: general 03 03 23 minimum clock cycle at cl= 4 3d 3d 24 maxi mum data access time from clock at cl= 4 50 50 25 minimum clock cycle time at cl=3 50 50 26 maximum data access time from clock at cl=3 60 60 27 minimum row precharge time (t r p ) 3c 32 28 minimum row active to row active delay (t r rd ) 28 28 29 minim um ??? to ??? delay (t r cd ) 3c 32 30 minimum active to precharge time (t ras ) 2d 2d 31 module r ank density 80 80 32 address and command setup time before clock (t is ) 20 17 33 address and command hold time after clock (t ih ) 27 25 34 data input setup ti me before clock (t ds ) 10 05 35 data input hold time after clock (tdh) 17 12 36 write recovery time (t wr ) 3c 3c
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 8 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detec t ( 1g b C 2 rank s , 64 mx16 ddr2 sdrams) (part 2 of 2) byte description serial pd data entry (hex.) note - 3c - ac 37 internal write to read command delay (t wtr ) 1e 1e 38 internal read to precharge delay (t rtp ) 1e 1e 39 reserved 00 00 40 extension of byte 41 t rc and byte 42 t rfc 06 36 41 minimum core cycle time (t rc ) 3c 39 42 min. auto refresh command cycle tim e (t rfc ) 7f 7f 43 maximum clock cycle time (t ck ) 80 80 44 max. dqs - dq skew factor (tqhs) 18 14 45 read data hold skew factor (tqhs) 22 1e 46 - 61 reserved -- -- 62 spd reversion 13 13 63 checksum for byte 0 - 62 a6 8c 64 - 71 manufacturers jedec id code -- -- 72 module manufacturing location 00 00 73 - 91 module part number -- -- 92 - 255 reserved -- --
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 9 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detec t ( 2 g b C 2 rank s , 128 mx 8 ddr2 sdrams) (part 1 of 2) byte description serial pd data entry (hex.) note - 3c - ac 0 n umber of serial pd bytes written during production 80 80 1 total number of bytes in serial pd device 08 08 2 fundamental memory type 08 08 3 number of row addresses on assembly 0e 0e 4 number of column addresses on assembly 0a 0a 5 number of dim m rank s , package, and height 61 61 6 data width of assembly 40 40 7 reserved 00 00 8 voltage interface level of this assembly 05 05 9 ddr2 sdram device cycle time at cl=5 30 25 10 ddr2 sdram device access time (t ac ) from clock at cl=5 45 40 11 dimm configuration type 00 00 12 refresh rate/type 82 82 13 primary ddr 2 sdram width 08 08 14 error checking ddr 2 sdram device width 00 00 15 reserved 00 00 16 ddr2 sdram device attributes: burst length supported 0c 0c 17 ddr2 sdram device attr ibutes: number of device banks 08 08 18 ddr2 sdram device attributes: ??? latencies supported 38 38 19 dimm mechanical characteristics 01 01 20 ddr2 sdram dimm type information 04 04 21 ddr2 sdram module attributes 00 00 22 ddr2 sdram device attributes: general 03 03 23 minimum clock cycle at cl= 4 3d 3d 24 maxi mum data access time from clock at cl= 4 50 50 25 minimum clock cycle time at cl=3 50 50 26 maximum data access time from clock at cl=3 60 60 27 minimum row precharge time ( t r p ) 3c 32 28 minimum row active to row active delay ( t r rd ) 1e 1e 29 minim um ??? to ??? delay ( t r cd ) 3c 32 30 minimum active to precharge time ( t ras ) 2d 2d 31 module r ank density 01 01 32 address and command setup time before clock (t is ) 20 17 33 address and command hold time after clock (t ih ) 27 25 34 data input setup ti me before clock (t ds ) 10 05 35 data input hold time after clock (tdh) 17 12 36 write recovery time (t wr ) 3c 3c
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 10 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. serial presence detec t ( 2 g b C 2 rank s , 128 m x 8 ddr2 sdrams) (part 2 of 2) byte description serial pd data entry (hex.) note - 3c - ac 37 internal write to read command delay (t wtr ) 1e 1e 38 internal read to precharge delay (t rtp ) 1e 1e 39 reserved 00 00 40 extension of byte 41 t rc and byte 42 t rfc 06 36 41 minimum core cycle time (t rc ) 3c 39 42 min. auto refresh command cycle time (t rfc ) 7f 7f 43 maximum clock cycle time (t ck ) 80 80 44 max. dqs - dq skew factor (tqhs) 18 14 45 read data hold skew factor (tqhs) 22 1e 46 - 61 reserved -- -- 62 spd reversion 13 13 63 checksum for byte 0 - 62 16 fc 64 - 71 manufacturers jed ec id code -- -- 72 module manufacturing location 00 00 73 - 91 module part number -- -- 92 - 255 reserved -- --
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 11 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. environmental requirements symbol parameter rating units t opr operating temperature (ambient) 0 to 65 c h opr operating humidity (relat ive) 10 to 90 % t stg storage temperature - 50 to 100 c h stg storage humidity (without condensation) 5 to 95 % barometric pressure (operating & storage) up to 9850ft. 105 to 69 kpa note : stress greater than those listed may cause permanent damage to t he device. this is a stress rating only and device functional operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect reliability absolute maximum dc ratings symbol pa rameter rating units v dd voltage on vdd pins relative to vss - 1.0 to +2.3 v v dd q voltage on vddq pins relative to vss - 0.5 to +2.3 v v ddl voltage on vddl pins relative to vss - 0.5 to +2.3 v v in , v out voltage on i/o pins relative to vss - 0.5 to +2.3 v t stg storage temperature (plastic) - 55 to +100 c note : stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec ti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. storage temperature is the case surface temperature on the cente r/top side of the dram. operating temperature conditions symbol parameter rating units note t case operating temperature (ambient) 0 to 95 c 1 note: 1. case temperature is measured at top and center side of any drams. 2. t case > 85 c ? t refi = 3.9 s dc electrical characteristics and operating conditions symbol parameter min max units notes v dd supply voltage 1.7 1.9 v 1 v ddl dll supply voltage 1.7 1.9 v 1 v dd q output supply voltage 1.7 1.9 v 1 v ss, v ssq supply voltage , i/o supply voltage 0 0 v v ref i nput reference voltage 0.49 v dd q 0.51 v dd q v 1, 2 v tt termination voltage v ref C 0.04 v ref + 0.04 v 3 note: 1. there is no specific device vdd supply voltage requirement for sstl_18 compliance. however, vddq must be less than or equal t o vdd unde r all conditions. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak - to - peak noise on v ref may not exceed 2% of the dc value. 3. vtt of transmitting device must track vref of receivi ng device.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 12 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. odt dc electrical characteristics parameter/condition symbol min. nom. max. units note rtt effective impedance value for emrs(a6,a2)=0,1; 75ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50ohm rtt3(eff) 40 50 60 ohm 1 deviation of v m with respect to vddq/2 delta vm - 6 +6 % 1 note1: test condition for rtt measurements. ` input ac/dc logic level symbol parameter pc2 - 5300 pc2 - 64 00 units min. max. min. max. v ih (ac) input high (logic1) voltage v ref + 0.20 0 - v ref + 0.20 0 - v v il (ac) input low (logic0) voltage - v ref C 0. 20 0 - v ref C 0. 20 0 v v ih (dc) input high (logic1) voltage v ref + 0.125 v ddq + 0.3 v ref + 0.125 v d dq + 0.3 v v il (dc) input low (logic0) voltage - 0.3 v ref C 0. 125 - 0.3 v ref C 0. 125 v
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 13 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0 .1v [ 1g b, 2 r ank s , 64 mx16 ddr 2 sdrams ] symbol parameter/condition pc2 - 5300 ( - 3 c ) p c2 - 6400 ( - a c ) unit idd0 operating current: one bank; active/precharge; t rc = t rc ( min) ; t ck = t ck ( min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 660 792 ma idd1 operating current: on e bank; active/read/precharge; burst = 4; t rc = t rc ( min) ; cl= 4; t ck = t ck ( min) ; i out = 0ma; address and control inputs changing once per clock cycle 748 858 ma idd 2p precharge power - down standby current: all banks idle; power - down mode; cke ? v il ( max) ; t ck = t ck ( min ) 79 79 ma idd2q precharge quiet standby current 440 528 ma idd2 n idle standby current: cs ? v ih ( min) ; all banks idle; cke ? v ih (min ) ; t ck = t ck ( min) ; address and control inputs changing once per clock cycle 440 572 ma idd3n active st andby current: one bank; active/precharge; cs ? v ih ( min) ; cke ? v ih ( min) ; t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 506 616 ma idd4r operating curre nt: one bank; burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 4; t ck = t ck ( min) ; i out = 0ma 880 1320 ma idd4w operating current: one bank; burst = 4; wr ites; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl= 4; t ck = t ck ( min ) 880 1320 ma idd 5b burst refresh current: t rc = t rfc ( min ) 1100 1210 ma idd6 self - refresh current: c ke ? 0.2v 79 79 ma idd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min) ; i out = 0ma. 1364 1738 ma note: module idd was calculated from component idd. it may differ from the actual measurement.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 14 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents t case = 0 c ~ 85 c; v ddq = v dd = 1.8v 0 .1v [ 2gb, 2 r ank s , 128 m x 8 ddr 2 sdrams ] symbol parameter/condition pc2 - 5300 ( - 3 c ) pc2 - 6400 ( - a c ) unit idd0 op erating current: one bank; active/precharge; t rc = t rc ( min) ; t ck = t ck ( min) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 836 968 ma idd1 operating current: one bank; active/read/prechar ge; burst = 4; t rc = t rc ( min) ; cl= 4; t ck = t ck ( min) ; i out = 0ma; address and control inputs changing once per clock cycle 924 1100 ma idd 2p precharge power - down standby current: all banks idle; power - down mode; cke ? v il ( max) ; t ck = t ck ( min ) 158 158 ma idd2q precharge quiet standby current 528 616 ma idd2 n idle standby current: cs ? v ih ( min) ; all banks idle; cke ? v ih (min ) ; t ck = t ck ( min) ; address and control inputs changing once per clock cycle 528 704 ma idd3n active standby current: one bank; active/precharge; cs ? v ih ( min) ; cke ? v ih ( min) ; t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 660 792 ma idd4r operating current: one bank; burst = 4; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 4; t ck = t ck ( min) ; i out = 0ma 1144 1408 ma idd4w operating current: one bank; burst = 4; write s; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl= 4; t ck = t ck ( min ) 1144 1408 ma idd 5b burst refresh current: t rc = t rfc ( min ) 1672 1892 ma idd6 self - refresh current: cke ? 0.2v 158 158 ma idd7 operating current: four bank; four bank interleaving with bl = 4, address and control inputs randomly changing; 50% of data changing at every transfer; t rc = t rc (min) ; i out = 0ma. 2112 2552 ma note: module idd was calculated from component idd. it may differ from the actual measurement.
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 15 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing speci fi cations for ddr 2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0 .1v; v dd = 1.8v 0.1 v, see ac characteristics) (part 1 of 2) symbol parameter - 3c - a c unit no te s min. max. min. max. t ac dq output access time from ck/ ?? dqsck dqs output access time from ck/ ?? ch ck high - level width 0.48 0.5 2 0.48 0.5 2 t ck t cl ck low - level width 0.48 0.5 2 0.48 0.5 2 t ck t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time min(tch(ab. s),tcl(abs)) - min(tch(ab. s),tcl(abs)) - t ck t ck clock cycle time 3 8 2.5 8 ns t dh dq and dm input hold time 175 - 125 - ps t ds dq an d dm input setup time 100 - 50 - ps t ipw input pulse width 0.6 - 0.6 - t ck t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - t ck t hz data - out high - impedance time from ck/ ?? ac max - t ac max ns t lz(dq) data - out low - impedance time from ck / ?? ac min t ac max 2 x t ac min t ac max ns t lz(dqs) dqs low - impedance time from ck/ ?? ac min t ac max t ac min t ac max ns t dqsq dqs - dq skew (dqs & associated dq signals) - 0.24 - 0.2 0 ns t qh s data hold skew factor - 0.34 - 0.30 ns t qh data output hold time from dqs t hp C qh s - t hp C qh s - ns t dqss write command to 1 st dqs latching transition - 0.25 0.25 - 0.25 0.25 t ck t dqs h dqs input high pulse width 0.35 - 0.35 - t ck t dqs l dqs input low pulse width 0.35 - 0.35 - t ck t dss dqs falling edge to ck setup time (write cycle) 0.2 - 0.2 - t ck t dsh dqs falling edge hold time from ck (write cycle) 0.2 - 0.2 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpst wr ite postamble 0.40 0.60 0.40 0.60 t ck t wpre write preamble 0. 3 5 - 0. 3 5 - t ck t ih address and control input hold time 0.275 - 0.250 - ns t is address and control input setup time 0.2 - 0.175 - ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.4 0.6 0.4 0.6 t ck t delay minimum time clocks remains on after cke asynchronously drops low t is + t ck (avg) + t ih - t is + t ck (avg) + t ih - ns t rfc refresh to active/refresh command time 127.5 1 27.5 ns t refi average periodic refresh interva l (85oc < t case 95oc) (0oc t case 85oc)
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 16 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac timing specifications for ddr 2 sdram devices used on module (t case = 0 c ~ 85 c; v ddq = 1.8v 0 .1v; v dd = 1.8v 0.1 v, see ac characteristics ) (part 2 of 2) symbol parameter - 3c - a c unit note s min. max. min. max. t rrd active bank a to active bank b command 7.5 - 7.5 - ns t ccd ??? ??? ck t wr write recovery time 15 - 15 - ns wr write recovery time with auto - precharge t wr /t ck t wr /t ck ns t dal auto precharge write recovery + precharge t ime wr +t n rp - wr +t n rp - t ck t wtr internal write to read command delay 7.5 - 7.5 - ns t rtp internal read to precharge command delay 7.5 - 7.5 - ns t xsn r exit self r efresh to a non - read command t rfc +10 - t rfc +10 - ns t xsrd exit self r efresh to a read command 200 - 200 - t ck t xp exit precharge power down to a ny non - read command 2 - 2 - t ck t xard exit active power down to read command 2 - 2 - t ck t xard s exit active power down to read command 7 - al - 8 - al - t ck t cke cke minimum pulse width 3 - 3 - t ck t oit ocd drive mode output delay 0 12 0 12 ns odt t aond odt turn - on delay 2 2 2 2 t ck t aon odt turn - on t ac (min) t ac (max) + 0.7 t ac (min) t ac (max) + 0.7 ns t aon p d odt turn - on ( power down mode) t ac (min) +2 2 t ck (avg) + t ac (max) +1 t ac (min) +2 2 t ck (avg) + t ac (max) +1 ns t a ofd odt turn - off delay 2.5 2.5 2.5 2.5 t ck t aof odt turn - off t ac (min) t ac (max) +0.6 t ac (min) t ac (max) +0.6 ns t aof p d odt turn - off (power down mode) t ac (min) +2 2.5t ck (avg) + t ac (max) +1 t ac (min) +2 2.5t ck (avg) + t ac (max) +1 ns t anpd odt to power down entry latency 3 - 3 - t ck t axpd odt power down exit latency 8 - 8 - t ck speed grade definition symbol parameter - 3c - a c unit min. max. min. max. t ras r ow active time 45 70000 45 70000 ns t rcd ras to cas delay 15 - 12.5 - ns t rc row cycle time 60 - 57.5 - ns t rp row precharge time 15 - 12.5 - ns
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 17 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [1g b C 2 r ank s , 64 mx16 ddr 2 sdrams ] note: device position and scale are only for reference. 6 7 . 6 0 f r o n t s i d e 1 9 9 1 3 9 4 1 d e t a i l a d e t a i l b 1 1 . 4 0 ( 2 x ) ? b a c k 6 3 . 6 0 d e t a i l a 2 . 5 5 0 . 6 0 d e t a i l b 0 . 4 5 n o t e : a l l d i m e n s i o n s a r e t y p i c a l w i t h t o l e r a n c e s o f + / - 0 . 1 5 u n l e s s o t h e r w i s e s t a t e d . u n i t s : m i l l i m e t e r s ( i n c h e s ) 4 . 0 0 + / - 0 . 1 0 1 . 0 0 + / - 0 . 1 0 . 2 5 m a x 3 . 8 0 m a x 1 . 0 0 + / - 0 . 1 0 2 . 4 5 4 7 . 4 0 2 . 7 0 4 . 2 0 2 . 1 5 1 . 8 0 4 . 0 0 2 0 . 0 0 3 0 . 0 0 6 . 0 0
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 18 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. package dimensions [2g b C 2 r ank s , 128 m x8 ddr 2 sdrams ] note: device position and scale are only for reference. 6 7 . 6 0 f r o n t s i d e 1 9 9 1 4 1 d e t a i l a d e t a i l b 4 . 0 0 2 0 . 0 0 3 0 . 0 0 6 . 0 0 ( 2 x ) ? b a c k 6 3 . 6 0 3 9 d e t a i l a 2 . 5 5 0 . 6 0 d e t a i l b 0 . 4 5 n o t e : a l l d i m e n s i o n s a r e t y p i c a l w i t h t o l e r a n c e s o f + / - 0 . 1 5 u n l e s s o t h e r w i s e s t a t e d . u n i t s : m i l l i m e t e r s ( i n c h e s ) 4 . 0 0 + / - 0 . 1 0 1 . 0 0 + / - 0 . 1 0 . 2 5 m a x 3 . 8 0 m a x 1 . 0 0 + / - 0 . 1 0 2 . 4 5 4 7 . 4 0 2 . 7 0 4 . 2 0 1 1 . 4 0 2 . 1 5 1 . 8 0
m2n1g64tuh8g5f / m2s1g64tuh8g4f / m2n2g64tu8hg5b / M2N2G64TU8HG4B 1gb: 128m x 64 / 2gb: 256m x 64 pc2 - 53 00 / pc2 - 6400 unbuffered ddr2 so - dimm re v 1.0 19 0 7 /20 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. revision log rev date modification 0 .1 0 1 /20 1 0 prelimin ary edition 1.0 07/2010 official release nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886 - 3 - 328 - 1688 please visit our home page for more information: http://www.elixir - memory.com printed in taiwan ? 20 10

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